OpenTimer v2: A New Parallel Incremental Timing Analysis Engine

Tsung-Wei Huang, Guannan Guo, Chun Xun Lin, Martin D.F. Wong

Research output: Contribution to journalArticlepeer-review

Abstract

Since the first release in 2015, OpenTimer v1 has been used in many industrial and academic projects for analyzing the timing of custom designs. After four-year research and developments, we have announced OpenTimer v2 – a major release that efficiently supports: (1) a new task-based parallel incremental timing analysis engine to break through the performance bottleneck of existing loop-based methods, (2) a new application programming interface (API) concept to exploit high degrees of parallelisms, (3) an enhanced support for industry standard design formats to improve user experience. Compared with OpenTimer v1, we rearchitect v2 with modern C++ programming language and advanced parallel computing techniques to largely improve the tool performance and usability. For a particular example, OpenTimer v2 achieved up to 5.33× speed-up over v1 in incremental timing, and scaled higher with increasing cores. Our contributions include both technical innovations and engineering knowledge that are open and accessible to promote timing research in the community.

Keywords

  • Logic gates
  • Optimization
  • Parallel processing
  • Pins
  • Task analysis
  • Timing
  • Tools

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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