TY - GEN
T1 - Online sharing-aware thread mapping in software transactional memory
AU - Pasqualin, Douglas Pereira
AU - Diener, Matthias
AU - Du Bois, Andre Rauber
AU - Pilla, Mauricio Lima
N1 - Funding Information:
This study was financed in part by the Coordenac¸ão de Aperfeic¸oamento de Pessoal de Nível Superior - Brasil (CAPES) - Finance Code 001 and PROCAD/LEAPaD
Publisher Copyright:
© 2020 IEEE.
PY - 2020/9
Y1 - 2020/9
N2 - Software Transactional Memory (STM) is an alternative abstraction to synchronize processes in parallel programming. One advantage is simplicity since it is possible to replace the use of explicit locks with atomic blocks. Regarding STM performance, many studies already have been made focusing on reducing the number of aborts. However, in current multicore architectures with complex memory hierarchies, it is also important to consider where the memory of a program is allocated and how it is accessed. This paper proposes the use of a technique called sharing-aware mapping, which maps threads to cores of an application based on their memory access behavior, to achieve better performance in STM systems. We introduce STMap, an online, low overhead mechanism to detect the sharing behavior and perform the mapping directly inside the STM library, by tracking and analyzing how threads perform STM operations. In experiments with the STAMP benchmark suite and synthetic benchmarks, STMap shows performance gains of up to 77% on a Xeon system (17.5% on average) and 85% on an Opteron system (9.1% on average), compared to the Linux scheduler.
AB - Software Transactional Memory (STM) is an alternative abstraction to synchronize processes in parallel programming. One advantage is simplicity since it is possible to replace the use of explicit locks with atomic blocks. Regarding STM performance, many studies already have been made focusing on reducing the number of aborts. However, in current multicore architectures with complex memory hierarchies, it is also important to consider where the memory of a program is allocated and how it is accessed. This paper proposes the use of a technique called sharing-aware mapping, which maps threads to cores of an application based on their memory access behavior, to achieve better performance in STM systems. We introduce STMap, an online, low overhead mechanism to detect the sharing behavior and perform the mapping directly inside the STM library, by tracking and analyzing how threads perform STM operations. In experiments with the STAMP benchmark suite and synthetic benchmarks, STMap shows performance gains of up to 77% on a Xeon system (17.5% on average) and 85% on an Opteron system (9.1% on average), compared to the Linux scheduler.
KW - Multicore
KW - Sharing-aware
KW - Software Transactional Memory
KW - Thread Mapping
UR - http://www.scopus.com/inward/record.url?scp=85095863089&partnerID=8YFLogxK
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U2 - 10.1109/SBAC-PAD49847.2020.00016
DO - 10.1109/SBAC-PAD49847.2020.00016
M3 - Conference contribution
AN - SCOPUS:85095863089
T3 - Proceedings - Symposium on Computer Architecture and High Performance Computing
SP - 35
EP - 42
BT - Proceedings - 2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2020
PB - IEEE Computer Society
T2 - 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2020
Y2 - 8 September 2020 through 11 September 2020
ER -