Online and operand-aware detection of failures utilizing false alarm vectors

Amir Yazdanbakhsh, David Palframan, Azadeh Davoodi, Nam Sung Kim, Mikko Lipasti

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This work presents a framework which detects online and at operand level of granularity all the vectors which excite a set of diagnosed failures in combinational modules. The failures may be of various types and may change over time. We propose to utilize this ability to detect failures at operand level of granularity to improve yield, by not discarding those chips containing failing and redundant computational units as long as they are not failing at the same time. The main challenge in realization of such a framework is the ability for on-chip storage of all the (test) vectors which excite the set of diagnosed failures. A major contribution of this work is to significantly minimize the number of stored test cubes by inserting only a few but carefully-selected "false alarm" vectors. As a result, a computational unit may be misdiagnosed as failing for a given operand however we show such cases are rare and the chip may continue to be used.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Number of pages6
ISBN (Electronic)9781450334747
StatePublished - May 20 2015
Externally publishedYes
Event25th Great Lakes Symposium on VLSI, GLSVLSI 2015 - Pittsburgh, United States
Duration: May 20 2015May 22 2015

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Other25th Great Lakes Symposium on VLSI, GLSVLSI 2015
Country/TerritoryUnited States


  • Manufacturing yield

ASJC Scopus subject areas

  • General Engineering

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