@misc{9abdc7dddbf44da3b94ae7a71e59e1d1,
title = "One billionTransistors, one uniprocessor, one chip",
abstract = "To achieve the highest performance possible, the billion transistors available on each chip should be utilized to support the highest performance uniprocessor, with the resulting chips interconnected to create a multiprocessor system.",
author = "Patt, {Yale N.} and Patel, {Sanjay J.} and Marius Evers and Friendly, {Daniel H.} and Jared Stark",
note = "Funding Information: The HPS execution model—aggressive microarchitecture in support of high-performance single-instruction streams—started in 1984 and has benefited enormously from the students who have worked on it since its inception. We particularly acknowledge the contributions of Wen-mei Hwu, Steve Melvin, Mike Shebanow, Tse-Yu Yeh, Mike Butler, Eric Hao, and Po-Yung Chang, whose PhD research greatly strengthened our understanding of the HPS paradigm. Also, we gratefully acknowledge the financial support of our industrial sponsors—in particular, Intel, NCR, and Motorola.",
year = "1997",
month = sep,
doi = "10.1109/2.612249",
language = "English (US)",
volume = "30",
pages = "51--57",
journal = "Computer",
issn = "0018-9162",
publisher = "IEEE Computer Society",
}