On timing closure: Buffer insertion for hold-violation removal

Pei Ci Wu, Martin D.F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Timing closure, which is to meet the design's timing con-straints, is a key problem in the physical design flow. Dur- ing the timing optimization process, buffers can be used to speedup the circuit or serve as delay elements. In this pa- per, we study the hold-violation removal problem for to- day's industrial designs. Discrete buffers, accurate timing models/analysis, and complex timing constraints make the problem difficult and time-consuming to solve. In this paper, we first present a linear programming-based methodology to model the setup and hold-time constraints. Then based on the solution to the linear programming, buffers are inserted as delay elements to solve hold violations. In the experiment, our approach is tested on industrial designs, then runs with the industrial optimization flow, and better results in terms of hold violations and runtime are reported.

Original languageEnglish (US)
Title of host publicationDAC 2014 - 51st Design Automation Conference, Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479930173
StatePublished - 2014
Event51st Annual Design Automation Conference, DAC 2014 - San Francisco, CA, United States
Duration: Jun 2 2014Jun 5 2014

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other51st Annual Design Automation Conference, DAC 2014
Country/TerritoryUnited States
CitySan Francisco, CA


  • Buffer insertion
  • Physical synthesis
  • Timing optimization

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation


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