### Abstract

The structural tree-based mapping algorithm is an efficient and popular technique for technology mapping. In order to make good use of this mapping technique, it is desirable to design FPGA logic modules based on Boolean functions which can be represented by a tree of gates (i.e. series-parallel or SP functions). In [5], the authors studied this issue and demonstrated the advantages of designing logic modules as universal SP functions, i.e. SP functions which can implement all SP functions with a certain number of inputs. However, the universal SP functions presented in [5] were designed manually and an automatic generation of universal SP functions was left as an open problem. In this paper, we present an algorithm to generate, for each n>0, a universal SP function for implementing all n-input SP functions. We also present an efficient Boolean matching algorithm for matching functions to the universal SP functions that we constructed. As it is important to have alternative universal SP functions from which logic-module designers can choose a design taking other criteria (e.g. area, delay, or power) into consideration, we developed an algorithm to generate alternative universal SP functions. In particular, we have found all universal SP functions for n-input SP functions, when n≤6.

Original language | English (US) |
---|---|

Title of host publication | Proceedings - IEEE International Conference on Computer Design |

Subtitle of host publication | VLSI in Computers and Processors |

Editors | Anon |

Publisher | IEEE |

Pages | 482-488 |

Number of pages | 7 |

State | Published - 1997 |

Externally published | Yes |

Event | Proceedings of the 1997 International Conference on Computer Design - Austin, TX, USA Duration: Oct 12 1997 → Oct 15 1997 |

### Other

Other | Proceedings of the 1997 International Conference on Computer Design |
---|---|

City | Austin, TX, USA |

Period | 10/12/97 → 10/15/97 |

### Fingerprint

### ASJC Scopus subject areas

- Hardware and Architecture
- Electrical and Electronic Engineering

### Cite this

*Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors*(pp. 482-488). IEEE.

**On the construction of universal series-parallel functions for logic module design.** / Young, F. Y.; Wong, Martin D F.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors.*IEEE, pp. 482-488, Proceedings of the 1997 International Conference on Computer Design, Austin, TX, USA, 10/12/97.

}

TY - GEN

T1 - On the construction of universal series-parallel functions for logic module design

AU - Young, F. Y.

AU - Wong, Martin D F

PY - 1997

Y1 - 1997

N2 - The structural tree-based mapping algorithm is an efficient and popular technique for technology mapping. In order to make good use of this mapping technique, it is desirable to design FPGA logic modules based on Boolean functions which can be represented by a tree of gates (i.e. series-parallel or SP functions). In [5], the authors studied this issue and demonstrated the advantages of designing logic modules as universal SP functions, i.e. SP functions which can implement all SP functions with a certain number of inputs. However, the universal SP functions presented in [5] were designed manually and an automatic generation of universal SP functions was left as an open problem. In this paper, we present an algorithm to generate, for each n>0, a universal SP function for implementing all n-input SP functions. We also present an efficient Boolean matching algorithm for matching functions to the universal SP functions that we constructed. As it is important to have alternative universal SP functions from which logic-module designers can choose a design taking other criteria (e.g. area, delay, or power) into consideration, we developed an algorithm to generate alternative universal SP functions. In particular, we have found all universal SP functions for n-input SP functions, when n≤6.

AB - The structural tree-based mapping algorithm is an efficient and popular technique for technology mapping. In order to make good use of this mapping technique, it is desirable to design FPGA logic modules based on Boolean functions which can be represented by a tree of gates (i.e. series-parallel or SP functions). In [5], the authors studied this issue and demonstrated the advantages of designing logic modules as universal SP functions, i.e. SP functions which can implement all SP functions with a certain number of inputs. However, the universal SP functions presented in [5] were designed manually and an automatic generation of universal SP functions was left as an open problem. In this paper, we present an algorithm to generate, for each n>0, a universal SP function for implementing all n-input SP functions. We also present an efficient Boolean matching algorithm for matching functions to the universal SP functions that we constructed. As it is important to have alternative universal SP functions from which logic-module designers can choose a design taking other criteria (e.g. area, delay, or power) into consideration, we developed an algorithm to generate alternative universal SP functions. In particular, we have found all universal SP functions for n-input SP functions, when n≤6.

UR - http://www.scopus.com/inward/record.url?scp=0031357426&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031357426&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0031357426

SP - 482

EP - 488

BT - Proceedings - IEEE International Conference on Computer Design

A2 - Anon, null

PB - IEEE

ER -