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On retiming for FPGA logic module minimization
Yao Ping Chen,
D. F. Wong
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Keyphrases
Logic Module
100%
Retiming
100%
Combinational
100%
Module Minimization
100%
Flip-flop
66%
Integer Programming
66%
Minimization Problem
33%
Constraint Matrix
33%
Linear Programming Relaxation
33%
Totally Unimodular
33%
Integer Linear Programming
33%
Sequential Circuits
33%
Retiming Technique
33%
Computer Science
Integer Program
100%
Field Programmable Gate Arrays
100%
Minimization Problem
50%
Linear Program
50%
Sequential Circuit
50%
Mathematics
Integer
100%
Matrix (Mathematics)
33%
Minimizes
33%
Minimization Problem
33%
Linear Program
33%