On retiming for FPGA logic module minimization

Y. P. Chen, D. F. Wong

Research output: Contribution to conferencePaperpeer-review

Abstract

In this paper, we consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a flip-flop is the only destination of its driving combinational block, then both the flip-flop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of registers that can not be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program.

Original languageEnglish (US)
Pages394-397
Number of pages4
StatePublished - Dec 1 1994
Externally publishedYes
EventProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA
Duration: Oct 10 1994Oct 12 1994

Other

OtherProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors
CityCambridge, MA, USA
Period10/10/9410/12/94

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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