On optimal board-level routing for FPGA-based logic emulation

Wai Kei Mak, D. F. Wong

Research output: Contribution to journalConference article

Abstract

In this paper, we consider a board-level routing problem which is applicable to FPGA-based logic emulation systems such as the Realizer system [3] and the Enterprise Emulation System [5] manufactured by Quickturn Systems. For the case where all nets are two-terminal nets, we present an O(n2)-time optimal algorithm where n is the number of nets. Our algorithm guarantees 100% routing completion if the number of inter-chip signal pins on each FPGA chip in the logic emulation system is less than or equal to the number of I/O pins on the chip. Our algorithm is based on iteratively finding Euler circuits in graphs. We also prove that the routing problem with multi-terminal nets is NP-complete.

Original languageEnglish (US)
Pages (from-to)552-556
Number of pages5
JournalProceedings - Design Automation Conference
DOIs
StatePublished - 1995
Externally publishedYes
EventProceedings of the 32nd Design Automation Conference - San Francisco, CA, USA
Duration: Jun 12 1995Jun 16 1995

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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