Abstract
The authors investigate the problem of cycle-stealing and its impact on the scheduling of tasks in processors with data input/output. They identify the parameters and policies that govern cycle-stealing and analyze its effects on real-time systems with hard deadlines. They study different policies to resolve memory across conflicts between the processor and I/O devices and compare their effectiveness in improving task schedulability. They investigate various memory interleaving schemes and the level of interleaving required to adequately counter the effects of cycle-stealing.
| Original language | English (US) |
|---|---|
| Title of host publication | Unknown Host Publication Title |
| Publisher | IEEE |
| Pages | 2-11 |
| Number of pages | 10 |
| ISBN (Print) | 0818608153 |
| State | Published - 1987 |
| Externally published | Yes |
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Networks and Communications