On-chip oscilloscope for signal integrity characterization of interconnects in 130nm CMOS technology

Pavle Milosevic, José E. Schutt-Ainé

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, the design of a prototype chip for signal integrity characterization in 130nm CMOS technology is discussed. Measurement results for several interconnect configurations are presented. The goal is to accurately capture and characterize the transmission line properties of deep-submicron interconnects in order to generate guidelines for multi-GHz clock rate designs.

Original languageEnglish (US)
Title of host publicationElectrical Performance of Electronic Packaging, EPEP 2008
Pages65-68
Number of pages4
DOIs
StatePublished - 2008
Event17th Conference on Electrical Performance of Electronic Packaging, EPEP 2008 - San Jose, CA, United States
Duration: Oct 27 2008Oct 29 2008

Publication series

NameElectrical Performance of Electronic Packaging, EPEP

Other

Other17th Conference on Electrical Performance of Electronic Packaging, EPEP 2008
Country/TerritoryUnited States
CitySan Jose, CA
Period10/27/0810/29/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'On-chip oscilloscope for signal integrity characterization of interconnects in 130nm CMOS technology'. Together they form a unique fingerprint.

Cite this