On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology

David Roberts, Sung Kim Nam, Trevor Mudge

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of current technologies, which is highly anticipated in processor on-chip caches manufactured with future nanometer scale technologies. Our most significant finding from this study is that the devices in on-chip memory cells cannot be scaled at the same rate as devices in logic circuits due to the increasing number of erroneous memory cells with voltage scaling, requiring strong fault-tolerance techniques. Second, we propose a technique to minimize performance impacts under aggressive technology and voltage scaling. It works by merging pairs of faulty cache lines to make good lines and performs better than TMR at high error rates and at lower cost. We also estimate up to 28% energy savings at low voltage, relative to a recent fault-tolerance scheme [1]

Original languageEnglish (US)
Title of host publicationProceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007
Pages570-578
Number of pages9
DOIs
StatePublished - Dec 1 2007
Externally publishedYes
Event10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 - Lubeck, Germany
Duration: Aug 29 2007Aug 31 2007

Publication series

NameProceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007

Other

Other10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007
CountryGermany
CityLubeck
Period8/29/078/31/07

Keywords

  • Cache
  • DVS
  • Device scaling
  • Fault-tolerance

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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