O(n) algorithm for transistor stacking with performance constraints

Bulent Basaran, Rob A. Rutenbar

Research output: Contribution to journalConference articlepeer-review


We describe a new constraint-driven stacking algorithm for diffusion area minimization of CMOS circuits. It employs an Eulerian trail finding algorithm that can satisfy analog-specific performance constraints. Our technique is superior to other published approaches both in terms of its time complexity and in the optimality of the stacks it produces. For a circuit with n transistors, the time complexity is O(n). All performance constraints are satisfied and, for a certain class of circuits, optimum stacking is guaranteed.

Original languageEnglish (US)
Pages (from-to)221-226
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA
Duration: Jun 3 1996Jun 7 1996

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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