NVP: Non-uniform voltage and pulse width settings for power efficient hybrid STT-RAM

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As technology scales down, the leakage power of SRAM based cache becomes a more critical source of power dissipation, particularly for large last level cache where leakage power is dominant. The emerging non-volatile spin transfer torque RAM (STT-RAM) is a candidate to substitute SRAM due to its low leakage power and high thermal stability. However, considerable high energy and long latency of write operations in STT-RAMs are barriers to their commercial adoption. To address this problem, we propose a hybrid non-uniform cache architecture (NUCA) by combining SRAMs and STT-RAMs with different operating voltage/pulse width settings. Operating at low voltage increases the probability of failure. To alleviate this, we propose a technique that reduces STT-RAM write access energy by lowering voltage while ensures correctness by either retrying the failed writes or increasing effective pulse width. Simulation results indicate overall 20-30% power gain for various workloads in hybrid cache architecture. This comes with less than 2% performance loss.

Original languageEnglish (US)
Title of host publication2014 International Green Computing Conference, IGCC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479961771
DOIs
StatePublished - Feb 10 2015
Externally publishedYes
Event2014 International Green Computing Conference, IGCC 2014 - Dallas, United States
Duration: Nov 3 2014Nov 5 2014

Publication series

Name2014 International Green Computing Conference, IGCC 2014

Conference

Conference2014 International Green Computing Conference, IGCC 2014
Country/TerritoryUnited States
CityDallas
Period11/3/1411/5/14

Keywords

  • Hybrid Cache Architecture
  • Low Power
  • NUCA
  • STT-RAM

ASJC Scopus subject areas

  • General Computer Science
  • Renewable Energy, Sustainability and the Environment

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