Noise-tolerant dynamic circuit design technique

Ganesh Balamurugan, Naresh R Shanbhag

Research output: Contribution to journalArticlepeer-review


A new circuit technique, referred to as the twin-transistor technique, for increasing the noise immunity of dynamic logic circuits is presented. This technique makes dynamic logic gates more tolerant to noise appearing at the gate inputs. A multiply-accumulate circuit has been designed and fabricated using a 0.35μm process to verify this technique. Experimental results indicate that the twin-transistor technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4X) with only a modest increase in power dissipation (15%) and no loss in throughput.

Original languageEnglish (US)
Pages (from-to)425-428
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - 2000

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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