Abstract
We present new macromodeling techniques for capturing the response of a CMOS logic gate to noise pulses at the input. Two approaches are presented. The first one is a robust mathematical model which enables the hierarchical generation of noise abstracts for circuits composed of the precharacterized cells. The second is a circuit equivalent model which generates accurate noise waveforms for arbitrarily shaped and timed multiple-input glitches, arbitrary loads, and external noise coupling.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 888-893 |
| Number of pages | 6 |
| Journal | Proceedings - Design Automation Conference |
| DOIs | |
| State | Published - 2004 |
| Event | Proceedings of the 41st Design Automation Conference - San Diego, CA, United States Duration: Jun 7 2004 → Jun 11 2004 |
Keywords
- Cell model
- Circuit-equivalent model
- Mathematical model
- Noise analysis
- Sensitivity
- Simulation
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering