Noise characterization of static CMOS gates

Rouwaida Kanj, Timothy Lehner, Bhavna Agrawal, Elyse Rosenbaum

Research output: Contribution to journalConference articlepeer-review


We present new macromodeling techniques for capturing the response of a CMOS logic gate to noise pulses at the input. Two approaches are presented. The first one is a robust mathematical model which enables the hierarchical generation of noise abstracts for circuits composed of the precharacterized cells. The second is a circuit equivalent model which generates accurate noise waveforms for arbitrarily shaped and timed multiple-input glitches, arbitrary loads, and external noise coupling.

Original languageEnglish (US)
Pages (from-to)888-893
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - 2004
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004


  • Cell model
  • Circuit-equivalent model
  • Mathematical model
  • Noise analysis
  • Sensitivity
  • Simulation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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