@inproceedings{0677079701b94f2d99c6519d3f08b9f1,
title = "Node-aware stencil communication for heterogeneous supercomputers",
abstract = "High-performance distributed computing systems increasingly feature nodes that have multiple CPU sockets and multiple GPUs. The communication bandwidth between these components is non-uniform. Furthermore, these systems can expose different communication capabilities between these components. For communication-heavy applications, optimally using these capabilities is challenging and essential for performance. Bespoke codes with optimized communication may be non-portable across run-time/software/hardware configurations, and existing stencil frameworks neglect optimized communication. This work presents node-aware approaches for automatic data placement and communication implementation for 3D stencil codes on multi-GPU nodes with non-homogeneous communication performance and capabilities. Benchmarking results in the Summit system show that choices in placement can result in a 20\% improvement in single-node exchange, and communication specialization can yield a further 6x improvement in exchange time in a single node, and a 16\% improvement at 1536 GPUs.",
keywords = "CUDA, Communication, GPU, Heterogeneous, MPI, Node, Stencil, Topology",
author = "Carl Pearson and Mert Hidayetoglu and Mohammad Almasri and Omer Anjum and Chung, \{I. Hsin\} and Jinjun Xiong and Hwu, \{Wen Mei W.\}",
note = "This work is supported by IBM-ILLINOIS Center for Cognitive Computing Systems Research (C3SR) - a research collaboration as part of the IBM AI Horizon Network. This work utilizes resources supported by the National Science Foundation{\textquoteright}s Major Research Instrumentation program, grant \#1725729, as well as the University of Illinois at Urbana-Champaign. This work was supported in part by the Center for Research on Intelligent Storage and Processing-in-memory (CRISP), one of six centers of JUMP, a Semiconductor Research Corporation program co-sponsored by DARPA. This work was supported in part by the Center for Applications Driving Architectures (ADA), one of six centers of JUMP, a Semiconductor Research Corporation program co-sponsored by DARPA. The authors would especially like to thank Dawei Mu and Rakesh Nagi for supporting initial experiments and providing valuable insight.; 34th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020 ; Conference date: 18-05-2020 Through 22-05-2020",
year = "2020",
month = may,
doi = "10.1109/IPDPSW50202.2020.00136",
language = "English (US)",
series = "Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "796--805",
booktitle = "Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020",
address = "United States",
}