Network flow modeling for escape routing on staggered pin arrays

Wu Pei-Ci Wu, Martin D.F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently staggered pin arrays are introduced for modern designs with high pin density. Although some studies have been done on escape routing for hexagonal arrays, the hexagonal array is only a special kind of staggered pin array. There exist other kinds of staggered pin arrays in current industrial designs, and the existing works cannot be extended to solve them. In this paper, we study the escape routing problem on staggered pin arrays. Network flow models are proposed to correctly model the capacity constraints of staggered pin arrays. Our models are guaranteed to find an escape routing satisfying the capacity constraints if there exists one. The correctness of these models lead to an optimal algorithm.

Original languageEnglish (US)
Title of host publication2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
Pages193-198
Number of pages6
DOIs
StatePublished - May 20 2013
Event2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan
Duration: Jan 22 2013Jan 25 2013

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
CountryJapan
CityYokohama
Period1/22/131/25/13

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Pei-Ci Wu, W., & Wong, M. D. F. (2013). Network flow modeling for escape routing on staggered pin arrays. In 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 (pp. 193-198). [6509595] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2013.6509595