Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads

Ashutosh Dhar, Sitao Huang, Jinjun Xiong, Damir Jamsek, Bruno Mesnet, Jian Huang, Nam Sung Kim, Wen Mei Hwu, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The slow down in Moore's Law has resulted in poor scaling of performance and energy. This slow down in scaling has been accompanied by the explosive growth of cognitive computing applications, creating a demand for high performance and energy efficient solutions. Amidst this climate, FPGA-based accelerators are emerging as a potential platform for deploying accelerators for cognitive computing workloads. However, the slow-down in scaling also limits the scaling of memory and I/O bandwidths. Additionally, a growing fraction of energy is spent on data transfer between off-chip memory and the compute units. Thus, now more than ever, there is a need to leverage near-memory and in-storage computing to maximize the bandwidth available to accelerators, and further improve energy efficiency. In this paper, we make the case for leveraging FPGAs in near-memory and in-storage settings, and present opportunities and challenges in such scenarios. We introduce a conceptual FPGA-based near-data processing architecture, and discuss innovations in architecture, systems, and compilers for accelerating cognitive computing workloads.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
PublisherIEEE Computer Society
Pages68-75
Number of pages8
ISBN (Electronic)9781538670996
DOIs
StatePublished - Jul 2019
Event18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 - Miami, United States
Duration: Jul 15 2019Jul 17 2019

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2019-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

Conference18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
CountryUnited States
CityMiami
Period7/15/197/17/19

Fingerprint

Field programmable gate arrays (FPGA)
Particle accelerators
Data storage equipment
Bandwidth
Data transfer
Energy efficiency
Innovation

Keywords

  • Cognitive-Computing
  • Deep-Learning
  • FPGA
  • In-Storage-Acceleration
  • NMA
  • Near-Memory-Acceleration

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Dhar, A., Huang, S., Xiong, J., Jamsek, D., Mesnet, B., Huang, J., ... Chen, D. (2019). Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads. In Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 (pp. 68-75). [8839401] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2019.00021

Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads. / Dhar, Ashutosh; Huang, Sitao; Xiong, Jinjun; Jamsek, Damir; Mesnet, Bruno; Huang, Jian; Kim, Nam Sung; Hwu, Wen Mei; Chen, Deming.

Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society, 2019. p. 68-75 8839401 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dhar, A, Huang, S, Xiong, J, Jamsek, D, Mesnet, B, Huang, J, Kim, NS, Hwu, WM & Chen, D 2019, Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads. in Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019., 8839401, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2019-July, IEEE Computer Society, pp. 68-75, 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, United States, 7/15/19. https://doi.org/10.1109/ISVLSI.2019.00021
Dhar A, Huang S, Xiong J, Jamsek D, Mesnet B, Huang J et al. Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads. In Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society. 2019. p. 68-75. 8839401. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). https://doi.org/10.1109/ISVLSI.2019.00021
Dhar, Ashutosh ; Huang, Sitao ; Xiong, Jinjun ; Jamsek, Damir ; Mesnet, Bruno ; Huang, Jian ; Kim, Nam Sung ; Hwu, Wen Mei ; Chen, Deming. / Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads. Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society, 2019. pp. 68-75 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).
@inproceedings{ef1369e168d347f58d3be5b36f1d84a0,
title = "Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads",
abstract = "The slow down in Moore's Law has resulted in poor scaling of performance and energy. This slow down in scaling has been accompanied by the explosive growth of cognitive computing applications, creating a demand for high performance and energy efficient solutions. Amidst this climate, FPGA-based accelerators are emerging as a potential platform for deploying accelerators for cognitive computing workloads. However, the slow-down in scaling also limits the scaling of memory and I/O bandwidths. Additionally, a growing fraction of energy is spent on data transfer between off-chip memory and the compute units. Thus, now more than ever, there is a need to leverage near-memory and in-storage computing to maximize the bandwidth available to accelerators, and further improve energy efficiency. In this paper, we make the case for leveraging FPGAs in near-memory and in-storage settings, and present opportunities and challenges in such scenarios. We introduce a conceptual FPGA-based near-data processing architecture, and discuss innovations in architecture, systems, and compilers for accelerating cognitive computing workloads.",
keywords = "Cognitive-Computing, Deep-Learning, FPGA, In-Storage-Acceleration, NMA, Near-Memory-Acceleration",
author = "Ashutosh Dhar and Sitao Huang and Jinjun Xiong and Damir Jamsek and Bruno Mesnet and Jian Huang and Kim, {Nam Sung} and Hwu, {Wen Mei} and Deming Chen",
year = "2019",
month = "7",
doi = "10.1109/ISVLSI.2019.00021",
language = "English (US)",
series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
publisher = "IEEE Computer Society",
pages = "68--75",
booktitle = "Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019",

}

TY - GEN

T1 - Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads

AU - Dhar, Ashutosh

AU - Huang, Sitao

AU - Xiong, Jinjun

AU - Jamsek, Damir

AU - Mesnet, Bruno

AU - Huang, Jian

AU - Kim, Nam Sung

AU - Hwu, Wen Mei

AU - Chen, Deming

PY - 2019/7

Y1 - 2019/7

N2 - The slow down in Moore's Law has resulted in poor scaling of performance and energy. This slow down in scaling has been accompanied by the explosive growth of cognitive computing applications, creating a demand for high performance and energy efficient solutions. Amidst this climate, FPGA-based accelerators are emerging as a potential platform for deploying accelerators for cognitive computing workloads. However, the slow-down in scaling also limits the scaling of memory and I/O bandwidths. Additionally, a growing fraction of energy is spent on data transfer between off-chip memory and the compute units. Thus, now more than ever, there is a need to leverage near-memory and in-storage computing to maximize the bandwidth available to accelerators, and further improve energy efficiency. In this paper, we make the case for leveraging FPGAs in near-memory and in-storage settings, and present opportunities and challenges in such scenarios. We introduce a conceptual FPGA-based near-data processing architecture, and discuss innovations in architecture, systems, and compilers for accelerating cognitive computing workloads.

AB - The slow down in Moore's Law has resulted in poor scaling of performance and energy. This slow down in scaling has been accompanied by the explosive growth of cognitive computing applications, creating a demand for high performance and energy efficient solutions. Amidst this climate, FPGA-based accelerators are emerging as a potential platform for deploying accelerators for cognitive computing workloads. However, the slow-down in scaling also limits the scaling of memory and I/O bandwidths. Additionally, a growing fraction of energy is spent on data transfer between off-chip memory and the compute units. Thus, now more than ever, there is a need to leverage near-memory and in-storage computing to maximize the bandwidth available to accelerators, and further improve energy efficiency. In this paper, we make the case for leveraging FPGAs in near-memory and in-storage settings, and present opportunities and challenges in such scenarios. We introduce a conceptual FPGA-based near-data processing architecture, and discuss innovations in architecture, systems, and compilers for accelerating cognitive computing workloads.

KW - Cognitive-Computing

KW - Deep-Learning

KW - FPGA

KW - In-Storage-Acceleration

KW - NMA

KW - Near-Memory-Acceleration

UR - http://www.scopus.com/inward/record.url?scp=85072960705&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85072960705&partnerID=8YFLogxK

U2 - 10.1109/ISVLSI.2019.00021

DO - 10.1109/ISVLSI.2019.00021

M3 - Conference contribution

AN - SCOPUS:85072960705

T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

SP - 68

EP - 75

BT - Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019

PB - IEEE Computer Society

ER -