TY - GEN
T1 - Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads
AU - Dhar, Ashutosh
AU - Huang, Sitao
AU - Xiong, Jinjun
AU - Jamsek, Damir
AU - Mesnet, Bruno
AU - Huang, Jian
AU - Kim, Nam Sung
AU - Hwu, Wen Mei
AU - Chen, Deming
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - The slow down in Moore's Law has resulted in poor scaling of performance and energy. This slow down in scaling has been accompanied by the explosive growth of cognitive computing applications, creating a demand for high performance and energy efficient solutions. Amidst this climate, FPGA-based accelerators are emerging as a potential platform for deploying accelerators for cognitive computing workloads. However, the slow-down in scaling also limits the scaling of memory and I/O bandwidths. Additionally, a growing fraction of energy is spent on data transfer between off-chip memory and the compute units. Thus, now more than ever, there is a need to leverage near-memory and in-storage computing to maximize the bandwidth available to accelerators, and further improve energy efficiency. In this paper, we make the case for leveraging FPGAs in near-memory and in-storage settings, and present opportunities and challenges in such scenarios. We introduce a conceptual FPGA-based near-data processing architecture, and discuss innovations in architecture, systems, and compilers for accelerating cognitive computing workloads.
AB - The slow down in Moore's Law has resulted in poor scaling of performance and energy. This slow down in scaling has been accompanied by the explosive growth of cognitive computing applications, creating a demand for high performance and energy efficient solutions. Amidst this climate, FPGA-based accelerators are emerging as a potential platform for deploying accelerators for cognitive computing workloads. However, the slow-down in scaling also limits the scaling of memory and I/O bandwidths. Additionally, a growing fraction of energy is spent on data transfer between off-chip memory and the compute units. Thus, now more than ever, there is a need to leverage near-memory and in-storage computing to maximize the bandwidth available to accelerators, and further improve energy efficiency. In this paper, we make the case for leveraging FPGAs in near-memory and in-storage settings, and present opportunities and challenges in such scenarios. We introduce a conceptual FPGA-based near-data processing architecture, and discuss innovations in architecture, systems, and compilers for accelerating cognitive computing workloads.
KW - Cognitive-Computing
KW - Deep-Learning
KW - FPGA
KW - In-Storage-Acceleration
KW - NMA
KW - Near-Memory-Acceleration
UR - http://www.scopus.com/inward/record.url?scp=85072960705&partnerID=8YFLogxK
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U2 - 10.1109/ISVLSI.2019.00021
DO - 10.1109/ISVLSI.2019.00021
M3 - Conference contribution
AN - SCOPUS:85072960705
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 68
EP - 75
BT - Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
PB - IEEE Computer Society
T2 - 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Y2 - 15 July 2019 through 17 July 2019
ER -