Nallatech in-socket FPGA front-side bus accelerator

Craig Steffen; Gildas Genest

doi:10.1109/MCSE.2010.45

Nallatech in-socket FPGA front-side bus accelerator

Craig Steffen, Gildas Genest

National Center for Supercomputing Applications (NCSA)

Research output: Contribution to journal › Article › peer-review

Abstract

Field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.

Original language	English (US)
Article number	5432303
Pages (from-to)	78-82
Number of pages	5
Journal	Computing in Science and Engineering
Volume	12
Issue number	2
DOIs	https://doi.org/10.1109/MCSE.2010.45
State	Published - Mar 2010

Keywords

Accelerators
Bandwidth
Compiler
Field-programmable gate arrays
Reconfigurable
Xeon
Xilinx

ASJC Scopus subject areas

General Computer Science
General Engineering

Online availability

10.1109/MCSE.2010.45

Library availability

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Cite this

@article{7836d402c51143d9b3e80e503f9e44c2,

title = "Nallatech in-socket FPGA front-side bus accelerator",

abstract = "Field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.",

keywords = "Accelerators, Bandwidth, Compiler, Field-programmable gate arrays, Reconfigurable, Xeon, Xilinx",

author = "Craig Steffen and Gildas Genest",

note = "Funding Information: This work was supported by the US National Science Foundation{\textquoteright}s Coop erative Agreement NSF OCI 05-25308 and Cooperative Support Agreement NSF OCI 04-38712, and the National Archives and Records Administration{\textquoteright}s NSF OCI 05-04064.",

year = "2010",

month = mar,

doi = "10.1109/MCSE.2010.45",

language = "English (US)",

volume = "12",

pages = "78--82",

journal = "Computing in Science and Engineering",

issn = "1521-9615",

publisher = "IEEE Computer Society",

number = "2",

}

TY - JOUR

T1 - Nallatech in-socket FPGA front-side bus accelerator

AU - Steffen, Craig

AU - Genest, Gildas

N1 - Funding Information: This work was supported by the US National Science Foundation’s Coop erative Agreement NSF OCI 05-25308 and Cooperative Support Agreement NSF OCI 04-38712, and the National Archives and Records Administration’s NSF OCI 05-04064.

PY - 2010/3

Y1 - 2010/3

N2 - Field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.

AB - Field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.

KW - Accelerators

KW - Bandwidth

KW - Compiler

KW - Field-programmable gate arrays

KW - Reconfigurable

KW - Xeon

KW - Xilinx

UR - http://www.scopus.com/inward/record.url?scp=77949921359&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949921359&partnerID=8YFLogxK

U2 - 10.1109/MCSE.2010.45

DO - 10.1109/MCSE.2010.45

M3 - Article

AN - SCOPUS:77949921359

SN - 1521-9615

VL - 12

SP - 78

EP - 82

JO - Computing in Science and Engineering

JF - Computing in Science and Engineering

IS - 2

M1 - 5432303

ER -

Nallatech in-socket FPGA front-side bus accelerator

Abstract

Keywords

ASJC Scopus subject areas

Online availability

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