The series-stacked buffer (SSB) is an active twice-line frequency energy decoupling buffer architecture in single-phase converters. It allows a large voltage ripple on the main energy buffering capacitor to improve the energy utilization ratio, and hence the overall power density. A bi-directional converter connected in series generates an equal but opposite ripple to regulate the dc-bus to a constant dc voltage with low overall ripple. This architecture has been demonstrated to achieve much higher power density than the electrolytic capacitor bank with equivalent dc-bus voltage ripple. In this work, we propose a methodology that quantifies and formalizes the SSB design process into a multi-objective optimization problem, from which the optimal design choices on the Pareto front under multiple operation constraints can be solved. Design constraints, modeling of objective functions, and optimization algorithms are discussed. With realistic hardware parameters and constraints, this methodology is applied to the SSB design for a 1.5-kW, 400-V dc-bus system. The corresponding Pareto front results are presented. Three high power density SSB hardware prototype are designed based on the Pareto front optimization results and experimentally verified.