Multi-chip heterogeneously integrated array of active three-terminal transistor lasers and passive photonic structures for electronic-photonic integration on silicon

John A. Carlson, John M. Dallesasse

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An array of active photonic devices is fabricated in unison after a heterogeneous integration process first metal-eutectically bonds these distinct materials as a distribution onto a silicon host wafer. The patterning out of heterogeneous materials followed by the formation of all photonic devices allows for wide-area fine-alignment without the need for discrete die alignment or placement. The integration process is designed as a CMOS-compatible, scalable method for bringing together distinct III-V epitaxial structures and optical-waveguiding epitaxial structures, demonstrating the capabilities of forming a multi-chip layer of photonic materials. Integrated GaAs-based vertical light-emitting transistors (LET) are designed and fabricated as the active devices whose third electrical terminal provides an electrical interconnect and thermal dissipation path to the silicon host wafer. The performance of these devices as both electrical transistors and spontaneous-emission optical devices is compared to their monolithically-integrated counterparts to investigate improvements in device characteristics when integrated onto silicon. The fabrication methods are modified and optimized for thin-film transferred materials and are then extended to transistor laser (TL) fabrication. Passive waveguiding structures are designed and simulated for coupling light from the active devices, and their fabrication scheme is presented such that it can be similarly performed with transferred materials. Work toward the demonstration of integrated transistor lasers is shown to represent progress toward an electronic-photonic circuit network. The combination of heterogeneous integration with three-terminal photonic structures enables an elegant solution to both packaging and signal interconnect constraints for the implementation of photonic logic in silicon photonics systems.

Original languageEnglish (US)
Title of host publicationSilicon Photonics XV
EditorsGraham T. Reed, Andrew P. Knights
PublisherSPIE
ISBN (Electronic)9781510633339
DOIs
StatePublished - 2020
EventSilicon Photonics XV 2020 - San Francisco, United States
Duration: Feb 3 2020Feb 6 2020

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume11285
ISSN (Print)0277-786X
ISSN (Electronic)1996-756X

Conference

ConferenceSilicon Photonics XV 2020
Country/TerritoryUnited States
CitySan Francisco
Period2/3/202/6/20

Keywords

  • CMOS-compatibility
  • Heterogeneous integration
  • Light-emitting transistor
  • Photonic logic
  • Transistor laser

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

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