MOS models for LIM transient simulations

Maryam Hajimiri, Jose E Schutt-Aine

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an approach for the transient simulation of circuits through the latency insertion model using advanced models for MOS transistors. By taking into account the dynamic charge storage effects in short-channel devices a more accurate simulation of high-speed digital and analog circuits via the latency insertion method can be performed. The approach makes use of the SPICE LEVEL 3 transistor model for MOSFETs. In addition the use of the latency insertion method allows better convergence and higher computational speed for the simulation. Several computer simulations are performed to validate the method. Results show improvement in accuracy by using the high-level models.

Original languageEnglish (US)
Title of host publication2015 IEEE 24th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages189-192
Number of pages4
ISBN (Electronic)9781479936410
DOIs
StatePublished - Dec 3 2015
Event24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015 - San Jose, United States
Duration: Oct 25 2015Oct 28 2015

Other

Other24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015
CountryUnited States
CitySan Jose
Period10/25/1510/28/15

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Keywords

  • capacitance
  • latency
  • LIM
  • MOSFET
  • simulation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Hajimiri, M., & Schutt-Aine, J. E. (2015). MOS models for LIM transient simulations. In 2015 IEEE 24th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015 (pp. 189-192). [7347159] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EPEPS.2015.7347159