MOS models for LIM transient simulations

Maryam Hajimiri; Jose E Schutt-Aine

doi:10.1109/EPEPS.2015.7347159

MOS models for LIM transient simulations

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an approach for the transient simulation of circuits through the latency insertion model using advanced models for MOS transistors. By taking into account the dynamic charge storage effects in short-channel devices a more accurate simulation of high-speed digital and analog circuits via the latency insertion method can be performed. The approach makes use of the SPICE LEVEL 3 transistor model for MOSFETs. In addition the use of the latency insertion method allows better convergence and higher computational speed for the simulation. Several computer simulations are performed to validate the method. Results show improvement in accuracy by using the high-level models.

Original language	English (US)
Title of host publication	2015 IEEE 24th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	189-192
Number of pages	4
ISBN (Electronic)	9781479936410
DOIs	https://doi.org/10.1109/EPEPS.2015.7347159
State	Published - Dec 3 2015
Event	24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015 - San Jose, United States Duration: Oct 25 2015 → Oct 28 2015

Other

Other	24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015
Country	United States
City	San Jose
Period	10/25/15 → 10/28/15

Keywords

capacitance
latency
LIM
MOSFET
simulation

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/EPEPS.2015.7347159

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Cite this

Hajimiri, M & Schutt-Aine, JE 2015, MOS models for LIM transient simulations. in 2015 IEEE 24th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015., 7347159, Institute of Electrical and Electronics Engineers Inc., pp. 189-192, 24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015, San Jose, United States, 10/25/15. https://doi.org/10.1109/EPEPS.2015.7347159

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abstract = "This paper presents an approach for the transient simulation of circuits through the latency insertion model using advanced models for MOS transistors. By taking into account the dynamic charge storage effects in short-channel devices a more accurate simulation of high-speed digital and analog circuits via the latency insertion method can be performed. The approach makes use of the SPICE LEVEL 3 transistor model for MOSFETs. In addition the use of the latency insertion method allows better convergence and higher computational speed for the simulation. Several computer simulations are performed to validate the method. Results show improvement in accuracy by using the high-level models.",

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AB - This paper presents an approach for the transient simulation of circuits through the latency insertion model using advanced models for MOS transistors. By taking into account the dynamic charge storage effects in short-channel devices a more accurate simulation of high-speed digital and analog circuits via the latency insertion method can be performed. The approach makes use of the SPICE LEVEL 3 transistor model for MOSFETs. In addition the use of the latency insertion method allows better convergence and higher computational speed for the simulation. Several computer simulations are performed to validate the method. Results show improvement in accuracy by using the high-level models.

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