MOPED: Orchestrating interprocess message data on CMPs

Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization due to conflicts and pollution. Explicit motion of data in these architectures, such as message passing, can provide hints about program behavior that can be used to hide latency and improve cache behavior. However, to make these models attractive, synchronization overhead and data copying must also be offloaded from the processors. In this paper, we describe a Message Orchestration and Performance Enhancement Device (MOPED) that provides hardware mechanisms to support state-of-the-art message passing protocols such as MPI. MOPED extends the per-processor cache controllers and coherence protocol to support message synchronization and management in hardware, to transfer message data efficiently without intermediate buffer copies, and to place useful data in caches in a timely manner. MOPED thus allows full overlap between communication and computation on the cores. We extended a 16-core full-system simulator based on Simics and FeS2. MOPED interacts with the directory controllers to orchestrate message data. We evaluated benefits to performance and coherence traffic by integrating MOPED into the MPICH runtime. Relative to unmodified MPI execution, MOPED reduces execution time of real applications (NAS Parallel Benchmarks) by 17-45% and of communication microbenchmarks (Intel's IMB) by 76-94%. Off-chip memory misses are reduced by 43-88% for applications and by 75-100% for microbenchmarks.

Original languageEnglish (US)
Title of host publicationProceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Number of pages10
StatePublished - 2011
Event17th International Symposium on High-Performance Computer Architecture, HPCA 2011 - San Antonio, TX, United States
Duration: Feb 12 2011Feb 16 2011

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897


Other17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Country/TerritoryUnited States
CitySan Antonio, TX

ASJC Scopus subject areas

  • Hardware and Architecture


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