Monolithic Integration of InAlAs/InGaAs/InP Enhancement- and Depletion-Mode High Electron Mobility Transistors

A. Mahajan, P. Fay, M. Arafa, G. Cueva, I. Adesida

Research output: Contribution to journalConference articlepeer-review


A process for the monolithic integration of enhance¬ment- and depletion-mode high electron mobility transistors (E/D-HEMTs) in the lattice-matched InAlAs/InGaAs/InP material system is reported for gate lengths ranging from 0.3 \un to 1.0 Mm. The E-HEMTs with a 0.3 urn gate length exhibit a threshold voltage of +187 mV and a maximum DC extrinsic transconductance of 625 mS/mm, while a threshold voltage of -443 mV and a transconductance of462 mS/mm are measured for D-HEMTs of the same gate length. Variations of threshold voltage for all devices under study was minimal, with the 0.3 jjm gate length devices showing a standard deviation of 12 mV for the D-HEMTs and only 7 mV for the E-HEMTs. The devices demonstrate excellent RF performance, with the 0.3 um E-HEMTs eJiJhibiting a unity current gain cutoff frequency (ft) of 95 GHz, and the 0.3 pm D-HEMTs yielding a nearly identical ft of 102 GHz. To the best of the authors' knowledge, this is the first report of high speed monolithically integrated E/D HEMTs on lattice-matched InP-based materials.

Original languageEnglish (US)
Pages (from-to)51-54
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: Dec 8 1996Dec 11 1996

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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