Monolithic barrier-all-around high electron mobility transistor with planar GaAs nanowire channel

Xin Miao, Chen Zhang, Xiuling Li

Research output: Contribution to journalArticle

Abstract

High-quality growth of planar GaAs nanowires (NWs) with widths as small as 35 nm is realized by comprehensively mapping the parameter space of group III flow, V/III ratio, and temperature as the size of the NWs scales down. Using a growth mode modulation scheme for the NW and thin film barrier layers, monolithically integrated AlGaAs barrier-all-around planar GaAs NW high electron mobility transistors (NW-HEMTs) are achieved. The peak extrinsic transconductance, drive current, and effective electron velocity are 550 μS/μm, 435 μA/μm, and ∼2.9 × 107 cm/s, respectively, at 2 V supply voltage with a gate length of 120 nm. The excellent DC performance demonstrated here shows the potential of this bottom-up planar NW technology for low-power high-speed very-large-scale-integration (VLSI) circuits.

Original languageEnglish (US)
Pages (from-to)2548-2552
Number of pages5
JournalNano letters
Volume13
Issue number6
DOIs
StatePublished - Jun 12 2013

Fingerprint

High electron mobility transistors
high electron mobility transistors
Nanowires
nanowires
VLSI circuits
Transconductance
very large scale integration
transconductance
barrier layers
aluminum gallium arsenides
direct current
high speed
Modulation
gallium arsenide
modulation
Thin films
Electrons
Networks (circuits)
Electric potential
electric potential

Keywords

  • GaAs
  • high-electron-mobility transistors
  • III-V
  • nanowire
  • VLSI

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Bioengineering
  • Chemistry(all)
  • Materials Science(all)
  • Mechanical Engineering

Cite this

Monolithic barrier-all-around high electron mobility transistor with planar GaAs nanowire channel. / Miao, Xin; Zhang, Chen; Li, Xiuling.

In: Nano letters, Vol. 13, No. 6, 12.06.2013, p. 2548-2552.

Research output: Contribution to journalArticle

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