Monolithic barrier-all-around high electron mobility transistor with planar GaAs nanowire channel

Xin Miao, Chen Zhang, Xiuling Li

Research output: Contribution to journalArticlepeer-review


High-quality growth of planar GaAs nanowires (NWs) with widths as small as 35 nm is realized by comprehensively mapping the parameter space of group III flow, V/III ratio, and temperature as the size of the NWs scales down. Using a growth mode modulation scheme for the NW and thin film barrier layers, monolithically integrated AlGaAs barrier-all-around planar GaAs NW high electron mobility transistors (NW-HEMTs) are achieved. The peak extrinsic transconductance, drive current, and effective electron velocity are 550 μS/μm, 435 μA/μm, and ∼2.9 × 107 cm/s, respectively, at 2 V supply voltage with a gate length of 120 nm. The excellent DC performance demonstrated here shows the potential of this bottom-up planar NW technology for low-power high-speed very-large-scale-integration (VLSI) circuits.

Original languageEnglish (US)
Pages (from-to)2548-2552
Number of pages5
JournalNano letters
Issue number6
StatePublished - Jun 12 2013


  • GaAs
  • high-electron-mobility transistors
  • III-V
  • nanowire
  • VLSI

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Bioengineering
  • General Chemistry
  • General Materials Science
  • Mechanical Engineering


Dive into the research topics of 'Monolithic barrier-all-around high electron mobility transistor with planar GaAs nanowire channel'. Together they form a unique fingerprint.

Cite this