Module Frequency Estimation and Noise Budget Limitations/Trade-Offs in Multichip Modules as a Function of CMOS Chips Integration

Ramesh Senthinathan, John L. Prince, Andreas C. Cangellaris

Research output: Contribution to journalArticlepeer-review

Abstract

A detailed investigation on the estimation of module clock frequency, and the limitations due to system noise containment was performed as a function of CMOS chip integration level of multichip assemblies. The objective of this study is to analyze the overall noise limitations, and to predict the system performance as a function of integration level. Results have demonstrated that unwanted coupled noise and simultaneous switching noise are a major degradation/limitation factor with high levels of integration in multichip modules (MCM's). This effect is especially a major limiting factor with scaled and reduced-supply-voltage CMOS chips. Closed-form equations are included to estimate the module frequency and the overall noise budget for MCM's. Design curves are shown for CMOS MCM system frequency, and noise budget limitations are discussed for various levels of chip integrations. Results from case studies on performance and noise limits of future workstation MCM's are explained.

Original languageEnglish (US)
Pages (from-to)478-483
Number of pages6
JournalIEEE Transactions on Components, Hybrids, and Manufacturing Technology
Volume16
Issue number5
DOIs
StatePublished - Aug 1993
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • General Engineering
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Module Frequency Estimation and Noise Budget Limitations/Trade-Offs in Multichip Modules as a Function of CMOS Chips Integration'. Together they form a unique fingerprint.

Cite this