Module Frequency Estimation and Noise Budget Limitations/Trade-Offs in Multichip Modules as a Function of CMOS Chips Integration

A detailed investigation on the estimation of module clock frequency, and the limitations due to system noise containment was performed as a function of CMOS chip integration level of multichip assemblies. The objective of this study is to analyze the overall noise limitations, and to predict the system performance as a function of integration level. Results have demonstrated that unwanted coupled noise and simultaneous switching noise are a major degradation/limitation factor with high levels of integration in multichip modules (MCM's). This effect is especially a major limiting factor with scaled and reduced-supply-voltage CMOS chips. Closed-form equations are included to estimate the module frequency and the overall noise budget for MCM's. Design curves are shown for CMOS MCM system frequency, and noise budget limitations are discussed for various levels of chip integrations. Results from case studies on performance and noise limits of future workstation MCM's are explained.