Modeling interconnects for post-CMOS devices and comparison with copper interconnects

Shaloo Rakheja, Azad Naeemi

Research output: Contribution to journalArticle

Abstract

Power dissipation in charge-based technology is the biggest roadblock toward miniaturizing circuits. Quantummechanical tunneling and subthreshold leakage current will ultimately limit scaling of silicon field-effect transistors. To continue Moore's law scaling, it is imperative that devices working with a state variable other than electron charge are sought for. Examples of alternate state variables include electron spins, pseudo-spins in graphene, direct and indirect excitons, plasmons, and phonons. At the same time, interconnection aspects of devices utilizing novel state variables must be considered early on. This paper provides a framework to quantify energy dissipation in interconnects for novel state variables. Models for energy per bit are then used along with previously derived models for delay of interconnects for novel state variables to compare performance and energy dissipation of novel interconnects with complementary metaloxidesemiconductor (CMOS) interconnects. Comparison results provide important insights into material, device, and circuit implications of post-CMOS technologies.

Original languageEnglish (US)
Article number5720298
Pages (from-to)1319-1328
Number of pages10
JournalIEEE Transactions on Electron Devices
Volume58
Issue number5
DOIs
StatePublished - May 1 2011
Externally publishedYes

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Keywords

  • Alternate state variable
  • excitons
  • interconnects
  • plasmonics
  • spintronics

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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