Modeling, extraction and simulation of CMOS I/O circuits under ESD stress

Tong Li, Ching Han Tsai, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journalConference article

Abstract

A CAD tool set for VLSI CMOS I/O circuit design is developed. It includes a circuit simulator, a layout extractor and a substrate resistance solver. This paper presents a new layout extractor for CMOS I/O circuits and a new method for modelling the substrate resistance. With these tools, for the first time, full I/O circuits can be simulated accurately at the circuit-level with the substrate-coupling effects taken into consideration. The CAD tools are demonstratively applied to an industrial circuit.

Original languageEnglish (US)
Pages (from-to)389-392
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume6
StatePublished - Jan 1 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: May 31 1998Jun 3 1998

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Networks (circuits)
Computer aided design
Substrates
Simulators

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Modeling, extraction and simulation of CMOS I/O circuits under ESD stress. / Li, Tong; Tsai, Ching Han; Rosenbaum, Elyse; Kang, Sung Mo.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 6, 01.01.1998, p. 389-392.

Research output: Contribution to journalConference article

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