Modeling and understanding of external latchup in CMOS technologies-part I: Modeling latchup trigger current

Farzan Farbiz, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.

Original languageEnglish (US)
Article number5875872
Pages (from-to)417-425
Number of pages9
JournalIEEE Transactions on Device and Materials Reliability
Volume11
Issue number3
DOIs
StatePublished - Sep 1 2011

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Substrates
Networks (circuits)
Testing

Keywords

  • Circuit models
  • guard rings (GRs)
  • latchup

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

Modeling and understanding of external latchup in CMOS technologies-part I : Modeling latchup trigger current. / Farbiz, Farzan; Rosenbaum, Elyse.

In: IEEE Transactions on Device and Materials Reliability, Vol. 11, No. 3, 5875872, 01.09.2011, p. 417-425.

Research output: Contribution to journalArticle

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