Modeling and understanding of external latchup in CMOS technologies-part I: Modeling latchup trigger current

Farzan Farbiz; Elyse Rosenbaum

doi:10.1109/TDMR.2011.2159504

Modeling and understanding of external latchup in CMOS technologies-part I: Modeling latchup trigger current

Research output: Contribution to journal › Article

Abstract

This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.

Original language	English (US)
Article number	5875872
Pages (from-to)	417-425
Number of pages	9
Journal	IEEE Transactions on Device and Materials Reliability
Volume	11
Issue number	3
DOIs	https://doi.org/10.1109/TDMR.2011.2159504
State	Published - Sep 1 2011

Keywords

Circuit models
guard rings (GRs)
latchup

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Safety, Risk, Reliability and Quality
Electrical and Electronic Engineering

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10.1109/TDMR.2011.2159504

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Farbiz, F., & Rosenbaum, E. (2011). Modeling and understanding of external latchup in CMOS technologies-part I: Modeling latchup trigger current. IEEE Transactions on Device and Materials Reliability, 11(3), 417-425. [5875872]. https://doi.org/10.1109/TDMR.2011.2159504

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