Abstract
This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.
| Original language | English (US) |
|---|---|
| Article number | 5875872 |
| Pages (from-to) | 417-425 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Device and Materials Reliability |
| Volume | 11 |
| Issue number | 3 |
| DOIs | |
| State | Published - Sep 1 2011 |
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Keywords
- Circuit models
- guard rings (GRs)
- latchup
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Safety, Risk, Reliability and Quality
- Electrical and Electronic Engineering
Cite this
Modeling and understanding of external latchup in CMOS technologies-part I : Modeling latchup trigger current. / Farbiz, Farzan; Rosenbaum, Elyse.
In: IEEE Transactions on Device and Materials Reliability, Vol. 11, No. 3, 5875872, 01.09.2011, p. 417-425.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Modeling and understanding of external latchup in CMOS technologies-part I
T2 - Modeling latchup trigger current
AU - Farbiz, Farzan
AU - Rosenbaum, Elyse
PY - 2011/9/1
Y1 - 2011/9/1
N2 - This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.
AB - This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.
KW - Circuit models
KW - guard rings (GRs)
KW - latchup
UR - http://www.scopus.com/inward/record.url?scp=80052629799&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80052629799&partnerID=8YFLogxK
U2 - 10.1109/TDMR.2011.2159504
DO - 10.1109/TDMR.2011.2159504
M3 - Article
AN - SCOPUS:80052629799
VL - 11
SP - 417
EP - 425
JO - IEEE Transactions on Device and Materials Reliability
JF - IEEE Transactions on Device and Materials Reliability
SN - 1530-4388
IS - 3
M1 - 5875872
ER -