Modeling and understanding of external latchup in CMOS technologies-part II: Minority carrier collection efficiency

Farzan Farbiz, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

The n-wells of the parasitic p-n-p-n devices found in a CMOS layout will collect excess minority carriers from the chip substrate, potentially triggering latchup. This paper presents a model for the minority carrier collection efficiency of a given substrate current injector and collector pair; the model captures the effects of spacing, supply voltage, temperature, and current level. The model further describes the quantitative reduction in collection efficiency obtained by using guard rings. A good fit of the model to measurement results is observed in four different CMOS technologies.

Original languageEnglish (US)
Article number5875873
Pages (from-to)426-432
Number of pages7
JournalIEEE Transactions on Device and Materials Reliability
Volume11
Issue number3
DOIs
StatePublished - Sep 1 2011

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Substrates
Electric potential
Temperature

Keywords

  • CMOS
  • collection efficiency
  • latchup
  • substrate current

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

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