Modeling and mitigation of jitter in multi-Gbps source-synchronous I/O links

Ganesh Balamurugan, Naresh R Shanbhag

Research output: Contribution to conferencePaper

Abstract

Jitter significantly limits the maximum achievable data rates (MADR) over high-speed source-synchronous I/O links. In this paper, we present a simple model that comprehends transmitter and receiver jitter in a source-synchronous I/O link. We show that the channel can have a significant impact on transmit jitter at high data rates, resulting in 1.1X-3.8X jitter amplification for typical cases. We quantify the performance degradation of transmit/receive equalization and multi-level modulation schemes, due to jitter in high-speed I/O links. We present two design techniques to mitigate the effect of jitter on performance - transmission of a slower source-synchronous clock, and jitter equalization. Both techniques can improve MADR by 13% when signaling over a 20 inches FR4 channel.

Original languageEnglish (US)
Pages254-260
Number of pages7
StatePublished - Dec 2 2003
EventProceedings: 21st International Conference on Computer Design ICCD 2003 - San Jose, CA, United States
Duration: Oct 13 2003Oct 15 2003

Other

OtherProceedings: 21st International Conference on Computer Design ICCD 2003
CountryUnited States
CitySan Jose, CA
Period10/13/0310/15/03

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Balamurugan, G., & Shanbhag, N. R. (2003). Modeling and mitigation of jitter in multi-Gbps source-synchronous I/O links. 254-260. Paper presented at Proceedings: 21st International Conference on Computer Design ICCD 2003, San Jose, CA, United States.