Modeling and mitigation of jitter in high-speed source-synchronous inter-chip communication systems

Ganesh Balamurugan, Naresh R Shanbhag

Research output: Contribution to journalConference article

Abstract

Jitter significantly limits the maximum achievable data rates (MADR) over high-speed source-synchronous I/O links. In this paper, we present a simple model that comprehends transmitter and receiver jitter in a source-synchronous I/O link. We show that the channel can have a significant impact on transmit jitter at high data rates, resulting in 1.1X-3.8X jitter amplification for typical cases. We quantify the performance degradation of transmit/receive equalization and multi-level modulation schemes, due to jitter in high-speed I/O links. We present two design techniques to mitigate the effect of jitter on performance - transmission of a slower source-synchronous clock, and jitter equalization. Both techniques can improve MADR by 13% when signaling over a 20 FR4 channel.

Original languageEnglish (US)
Pages (from-to)1681-1687
Number of pages7
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
Volume2
StatePublished - Dec 1 2003
EventConference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States
Duration: Nov 9 2003Nov 12 2003

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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