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Model reduction for PEEC models including retardation
J. Cullum
, A. E. Ruehli
,
T. Zhang
Research output
:
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›
Paper
›
peer-review
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Keyphrases
Retardation
100%
Equivalent Circuit Model
100%
Partial Element Equivalent Circuit
100%
Model Reduction
100%
Two Dimensional Model
20%
Three-dimensional Problems
20%
Model Order Reduction
20%
Reduction Method
20%
Equivalent Circuit
20%
Engineering
Retardation
100%
Equivalent Circuit Model
100%
Model Reduction
100%
Equivalent Circuit
50%
Two Dimensional
25%
Interconnects
25%
Dimensional Problem
25%
Dimensional Model
25%
Mathematics
Equivalent Element
100%
Circuit Model
100%
Wide Range
20%
Dimensional Problem
20%
Dimensional Model
20%
Applicable Procedure
20%