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Minimizing wire length in floorplanning
Xiaoping Tang
, Ruiqi Tian
,
Martin D.F. Wong
Electrical and Computer Engineering
Research output
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Article
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peer-review
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Keyphrases
Floorplanning
100%
Wirelength
100%
Linear Programming
40%
Flow-based
20%
First-order
20%
Input-output
20%
Polynomial Time
20%
Compaction
20%
Good for
20%
Abutment
20%
White Space
20%
Block Boundary
20%
Microelectronic Center of North Carolina
20%
Minimum Area
20%
Soft Blocks
20%
Preplaced
20%
Rectilinear Blocks
20%
Block Placement
20%
Fixed Frame
20%
Compact Blocks
20%
Minimum Cost Flow
20%
Engineering
Linear Programming
100%
One Dimensional
50%
Experimental Result
50%
Microelectronics
50%
Optimality
50%
Abutment
50%
Polynomial Time
50%
Fixed Frame
50%
Block Boundary
50%
Output Pin
50%
Computer Science
Floorplanning
100%
Total Wirelength
100%
Linear Programming
100%
Experimental Result
50%
Input/Output
50%
Polynomial Time
50%
White Space
50%
Compact Floorplan
50%
Mathematics
Linear Programming
100%
Optimality
50%
Polynomial Time
50%
Rectilinear
50%