Microprocessor sensitivity to failures: Control vs. execution and combinational vs. sequential logic

Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew T Kalbarczyk, Ravishankar K Iyer

Research output: Contribution to conferencePaper

Abstract

The goal of this study is to characterize the impact of soft errors on embedded processors. We focus on control versus speculation logic on one hand, and combinational versus sequential logic on the other. The target system is a gate-level implementation of a DLX-like processor. The synthesized design is simulated, and transients are injected to stress the processor while it is executing selected applications. Analysis of the collected data shows that fault sensitivity of the combinational logic (4.2% for a fault duration of one clock cycle) is not negligible, even though it is smaller than the fault sensitivity of flip-flops (10.4%). Detailed study of the error impact, measured at the application level, reveals that errors in speculation and control blocks collectively contribute to about 34% of crashes, 34% of fail-silent violations and 69% of application incomplete executions. These figures indicate the increasing need for processor-level detection techniques over generic methods, such as ECC and parity, to prevent such errors from propagating beyond the processor boundaries.

Original languageEnglish (US)
Pages760-769
Number of pages10
DOIs
StatePublished - Nov 9 2005
Event2005 International Conference on Dependable Systems and Networks - Yokohama, Japan
Duration: Jun 28 2005Jul 1 2005

Other

Other2005 International Conference on Dependable Systems and Networks
CountryJapan
CityYokohama
Period6/28/057/1/05

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

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    Saggese, G. P., Vetteth, A., Kalbarczyk, Z. T., & Iyer, R. K. (2005). Microprocessor sensitivity to failures: Control vs. execution and combinational vs. sequential logic. 760-769. Paper presented at 2005 International Conference on Dependable Systems and Networks, Yokohama, Japan. https://doi.org/10.1109/DSN.2005.63