Microarchitectural power modeling techniques for deep sub-micron microprocessors

Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd Austin, Trevor Mudge

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance has moved to the fore. To satisfy this demand several microarchitectural power simulators have been developed around SimpleScalar, a widely used microarchitectural performance simulator. They have proven to be very useful at providing insights into power/performance trade-offs. However, they are neither parameterized nor technology scalable. In this paper, we propose more accurate parameterized power modeling techniques reflecting the actual technology parameters as well as input switching-events for memory and execution units. Compared to HSPICE, the proposed techniques show 93% and 91% accuracies for those blocks, but with a much faster simulation time. We also propose a more realistic power modeling technique for external I/O. In general, our approach includes more detailed microarchitectural and circuit modeling than has been the case in earlier simulators, without incurring a significant simulation time overhead-it can be as small as a few percent.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
PublisherAssociation for Computing Machinery
Pages212-217
Number of pages6
ISBN (Print)1581139292, 9781581139297
DOIs
StatePublished - 2004
Externally publishedYes
EventProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 - Newport Beach, CA, United States
Duration: Aug 9 2004Aug 11 2004

Publication series

NameProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Other

OtherProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
CountryUnited States
CityNewport Beach, CA
Period8/9/048/11/04

Keywords

  • Deep sub-micron
  • Power modeling

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Kim, N. S., Kgil, T., Bertacco, V., Austin, T., & Mudge, T. (2004). Microarchitectural power modeling techniques for deep sub-micron microprocessors. In Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 (pp. 212-217). [8.1] (Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04). Association for Computing Machinery. https://doi.org/10.1145/1013235.1013290