Microarchitectural Power Modeling Techniques for Deep Sub-Micron Microprocessors

Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd Austin, Trevor Mudge

Research output: Contribution to journalConference articlepeer-review


The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance has moved to the fore. To satisfy this demand several microarchitectural power simulators have been developed around SimpleScalar, a widely used microarchitectural performance simulator. They have proven to be very useful at providing insights into power/performance trade-offs. However, they are neither parameterized nor technology scalable. In this paper, we propose more accurate parameterized power modeling techniques reflecting the actual technology parameters as well as input switching-events for memory and execution units. Compared to HSPICE, the proposed techniques show 93% and 91% accuracies for those blocks, but with a much faster simulation time. We also propose a more realistic power modeling technique for external I/O. In general, our approach includes more detailed microarchitectural and circuit modeling than has been the case in earlier simulators, without incurring a significant simulation time overhead-it can be as small as a few percent.

Original languageEnglish (US)
Article number1349338
Pages (from-to)212-217
Number of pages6
JournalProceedings of the International Symposium on Low Power Electronics and Design
Issue numberJanuary
StatePublished - 2004
Externally publishedYes
Event2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States
Duration: Aug 9 2004Aug 11 2004


  • Deep sub-micron
  • Power modeling

ASJC Scopus subject areas

  • General Engineering


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