Methodology for rapid estimation of substrate-coupled switching noise

Sujoy Mitra, R. A. Rutenbar, L. R. Carley, D. J. Allstot

Research output: Contribution to journalConference articlepeer-review


In this paper we present a methodology for rapid estimation of substrate coupled switching noise in mixed-signal chips. This methodology differs from existing approaches in that it does not require full chip, SPICE level transient or frequency domain simulations or long user-specified test vectors at the chip I/O. Instead, it relies on power dissipation data available from system-level power estimators and determines an estimate of the substrate coupled switching noise profile on the chip-substrate. This method trades off the accuracy available in existing approaches for improved execution times and significantly simpler user-inputs. Thus, this methodology is useful when rough estimates of substrate coupled switching-noise are adequate, for example, during manual or automatic system-level mixed-signal floorplanning.

Original languageEnglish (US)
Pages (from-to)129-132
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - 1995
Externally publishedYes
EventProceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: May 1 1995May 4 1995

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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