A method of forming a nanoscale three-dimensional pattern in a porous semiconductor includes providing a film comprising a semiconductor material and defining a nanoscale metal pattern on the film, where the metal pattern has at least one lateral dimension of about 100 nm or less in size. Semiconductor material is removed from below the nanoscale metal pattern to create trenches in the film having a depth-to-width aspect ratio of at least about 10:1, while pores are formed in remaining portions of the film adjacent to the trenches. A three-dimensional pattern having at least one nanoscale dimension is thus formed in a porous semiconductor, which may be porous silicon. The method can be extended to form self-integrated porous low-k dielectric insulators with copper interconnects, and may also facilitate wafer level chip scale packaging integration.
|Original language||English (US)|
|U.S. patent number||8486843|
|State||Published - Jul 16 2013|