Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers

Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un Ku Moon

Research output: Contribution to journalArticlepeer-review

Abstract

An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13$\ \mu\hbox{m}$ CMOS technology, the prototype chip measures less than $\pm$4% variation in $K-{\rm VCO} \cdot I-{\rm CP} / N$ (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz.

Original languageEnglish (US)
Article number4768902
Pages (from-to)427-435
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number2
DOIs
StatePublished - Feb 2009
Externally publishedYes

Keywords

  • Bandwidth tracking
  • Frequency synthesizer
  • LC-VCO
  • Loop bandwidth
  • Phase-locked loop (PLL)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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