Merit-based characterization of assertions in hardware design verification

A system is configured to generate assertions for verification of an integrated circuit hardware design expressed at a register transfer level (RTL) for variables of interest, each including an antecedent and a consequent. A relative importance score for the variables is determined by characterizing respective variables by a level of importance with respect to a target variable of the consequent. The relative importance scores may be combined to form a relative importance score of the assertion. A relative complexity score for the variable is determined by characterizing the variable by a level of understandability of the variable with respect to the target variable. The relative complexity scores are combined to form a relative complexity score of the assertion. The relative importance and complexity scores are combined to generate a rank score, which is used in ranking the assertion with respect to the RTL design for which the assertion was generated.