Merging state and preserving timing anomalies in pipelines of high-end processors

Computer Science

• And-States 100%
• Out-of-Order Processor 100%
• Analysis Technique 50%
• Embedded Systems 50%
• Temporal Constraint 50%
• Real Time Systems 50%
• Instruction Scheduling 50%
• Static Program Analysis 50%
• Processor Architectures 50%
• Pipeline Processor 50%
• Modern Processor 50%
• Timing Behavior 50%

Keyphrases

• Pipeline Analysis 100%
• Timing Anomalies 100%
• Out-of-order Processors 66%
• Static Analysis 33%
• Embedded Systems 33%
• Timing Behavior 33%
• Pipeline Effect 33%
• Temporal Constraints 33%
• Hardware Complexity 33%
• Real-time Systems 33%
• Worst-case Behavior 33%
• Architectural Complexity 33%
• Instruction Scheduling 33%
• Processor Architecture 33%
• Nondeterminism 33%