Memory scheduling towards high-throughput cooperative heterogeneous computing

Hao Wang, Ripudaman Singh, Michael J. Schulte, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Technology scaling enables the integration of both the CPU and the GPU into a single chip for higher throughput and energy efficiency. In such a single-chip heterogeneous processor (SCHP), its memory bandwidth is the most critically shared resource, requiring judicious management to maximize the throughput. Previous studies on memory scheduling for SCHPs have focused on the scenario where multiple applications are running on the CPU and the GPU respectively, which we denote as a multi-tasking scenario. However, another increasingly important usage scenario for SCHPs is cooperative heterogeneous computing, where a single parallel application is partitioned between the CPU and the GPU such that the overall throughput is maximized. In previous studies on memory scheduling techniques for chip multi-processors (CMPs) and SCHPs, the first-ready first-come-first-service (FR-FCFS) scheduling policy was used as an inept baseline due to its fairness issue. However, in a cooperative heterogeneous computing scenario, we first demonstrate that FR-FCFS actually offers nearly 10% higher throughput than two recently proposed memory scheduling techniques designed for a multi-tasking scenario. Second, based on our analysis on memory access characteristics in a cooperative heterogeneous computing scenario, we propose various optimization techniques that enhance the row-buffer locality by 10%, reduce the service latency of CPU memory requests by 26%, and improve the overall throughput by up to 8% compared to FR-FCFS.

Original languageEnglish (US)
Title of host publicationPACT 2014 - Proceedings of the 23rd International Conference on Parallel Architectures and Compilation Techniques
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages331-341
Number of pages11
ISBN (Print)9781450328098
DOIs
StatePublished - Jan 1 2014
Event23rd International Conference on Parallel Architectures and Compilation Techniques, PACT 2014 - Edmonton, AB, Canada
Duration: Aug 24 2014Aug 27 2014

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Other

Other23rd International Conference on Parallel Architectures and Compilation Techniques, PACT 2014
CountryCanada
CityEdmonton, AB
Period8/24/148/27/14

Keywords

  • heterogeneous processor
  • memory scheduling

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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    Wang, H., Singh, R., Schulte, M. J., & Kim, N. S. (2014). Memory scheduling towards high-throughput cooperative heterogeneous computing. In PACT 2014 - Proceedings of the 23rd International Conference on Parallel Architectures and Compilation Techniques (pp. 331-341). (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2628071.2628096