Dopant pile-up within 1-2 nm of Si/SiO 2 interfaces during post-implant annealing can influence the performance of microelectronic devices using silicon-on-insulator technology or super-steep retrograde channels. Pile-up results from changes in the dopant interstitial charge state induced by band bending at the interface. But, there exists little mechanistic understanding of the specific conditions needed for pile-up or of the kinetics of temporal evolution. The present work uses continuum simulations coupled with experiments in the case of B implanted into Si to show that pile-up requires a zone near the interface wherein the Fermi level exceeds the ionization level for dopant interstitials to change their charge state. The spatial extent of pile-up corresponds closely to the width of this zone unless the annihilation probability of defects at the interface is large. The time and temperature dependences of pile-up closely track those of the free dopant interstitials concentration.
ASJC Scopus subject areas
- Physics and Astronomy(all)