Abstract
On-chip supply noise induced by power-on ESD is studied with the aid of on-chip monitor circuits and circuit simulation. The monitor circuits' outputs provide information about the magnitudes of the ESD-induced supply noise. The supply noise monitor circuits were implemented on a 130-nm CMOS test chip. Voltage monitor circuits record the maximum and minimum supply voltage excursions. Flip-flop monitor circuits respond to a rapid voltage change at the supply. Circuit simulation is used to validate hypotheses about how the noise spreads throughout the power delivery network.
Original language | English (US) |
---|---|
Article number | 8640259 |
Pages (from-to) | 211-220 |
Number of pages | 10 |
Journal | IEEE Transactions on Device and Materials Reliability |
Volume | 19 |
Issue number | 1 |
DOIs | |
State | Published - Mar 2019 |
Keywords
- System-level ESD
- on-chip monitor
- supply noise
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Safety, Risk, Reliability and Quality
- Electrical and Electronic Engineering