Measurement and simulation of on-chip supply noise induced by system-level ESD

Yang Xiu, Nicholas Thomson, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

On-chip supply noise induced by power-on ESD is studied with the aid of on-chip monitor circuits and circuit simulation. The monitor circuits' outputs provide information about the magnitudes of the ESD-induced supply noise. The supply noise monitor circuits were implemented on a 130-nm CMOS test chip. Voltage monitor circuits record the maximum and minimum supply voltage excursions. Flip-flop monitor circuits respond to a rapid voltage change at the supply. Circuit simulation is used to validate hypotheses about how the noise spreads throughout the power delivery network.

Original languageEnglish (US)
Article number8640259
Pages (from-to)211-220
Number of pages10
JournalIEEE Transactions on Device and Materials Reliability
Volume19
Issue number1
DOIs
StatePublished - Mar 2019

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Networks (circuits)
Circuit simulation
Electric potential
Flip flop circuits

Keywords

  • System-level ESD
  • on-chip monitor
  • supply noise

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

Measurement and simulation of on-chip supply noise induced by system-level ESD. / Xiu, Yang; Thomson, Nicholas; Rosenbaum, Elyse.

In: IEEE Transactions on Device and Materials Reliability, Vol. 19, No. 1, 8640259, 03.2019, p. 211-220.

Research output: Contribution to journalArticle

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