Massively parallel switch-level simulation: A feasibility study

Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar

Research output: Contribution to journalConference articlepeer-review

Abstract

The authors address the feasibility of mapping the COSMOS switch-level simulator onto a computer with thousands of simple processors. COSMOS preprocesses transistor networks into Boolean behavioral models, capturing the switch-level behavior of a circuit in a set of Boolean formulas. The authors describe a class of massively parallel computers and a mapping of COSMOS onto these computers. The factors affecting the performance of such a massively parallel simulator, including the amount of parallelism in the simulation model, performance measures for massively parallel machines, and the impact of event scheduling on simulator performance, are discussed. Compilation tools which automatically map a MOS circuit onto a massively parallel computer have been developed. Massively parallel switch-level simulation is illustrated by a description of a pilot implementation on a 32K processor Thinking Machines Connection Machine system.

Original languageEnglish (US)
Pages (from-to)91-97
Number of pages7
JournalProceedings - Design Automation Conference
DOIs
StatePublished - 1989
Event26th ACM/IEEE Design Automation Conference - Las Vegas, NV, USA
Duration: Jun 25 1989Jun 29 1989

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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