Mask cost reduction with circuit performance consideration for self-aligned double patterning

Hongbo Zhang, Yuelin Du, Martin D.F. Wong, Kai Yuan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Double patterning lithography (DPL) is the enabling technology for printing in sub-32nm nodes. In the EDA literature, researchers have been focusing on double-exposure double-patterning (DEDP) DPL for printing arbitrary 2D features where the layout decomposition problem for double exposure is an interesting graph coloring problem. But due to overlay errors, it is very difficult for DEDP to print even 1D features. A more promising DPL technology is self-aligned double patterning (SADP) for 1D design. SADP first prints dense lines and then trims away the portions not on the design by a cut mask. The complexity of cut mask is very high, adding to the skyrocketing manufacturing cost. In this paper we present a mask cost reduction method with circuit performance consideration for SADP. This is the first paper to focus on the mask cost reduction issue for SADP from a design perspective. We simplify the polygons on the cut mask, by formulating the problem as a constrained shortest path problem. Experimental results show that with a set of layouts in 28nm technology, we can largely reduce the complexity of cut polygons, with little impact on performance.

Original languageEnglish (US)
Title of host publication2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Pages787-792
Number of pages6
DOIs
StatePublished - Mar 28 2011
Event2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan
Duration: Jan 25 2011Jan 28 2011

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
CountryJapan
CityYokohama
Period1/25/111/28/11

Fingerprint

Cost reduction
Masks
Networks (circuits)
Lithography
Printing
Coloring
Decomposition
Costs

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Zhang, H., Du, Y., Wong, M. D. F., & Chao, K. Y. (2011). Mask cost reduction with circuit performance consideration for self-aligned double patterning. In 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 (pp. 787-792). [5722296] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2011.5722296

Mask cost reduction with circuit performance consideration for self-aligned double patterning. / Zhang, Hongbo; Du, Yuelin; Wong, Martin D.F.; Chao, Kai Yuan.

2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. 2011. p. 787-792 5722296 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, H, Du, Y, Wong, MDF & Chao, KY 2011, Mask cost reduction with circuit performance consideration for self-aligned double patterning. in 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011., 5722296, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 787-792, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, 1/25/11. https://doi.org/10.1109/ASPDAC.2011.5722296
Zhang H, Du Y, Wong MDF, Chao KY. Mask cost reduction with circuit performance consideration for self-aligned double patterning. In 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. 2011. p. 787-792. 5722296. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2011.5722296
Zhang, Hongbo ; Du, Yuelin ; Wong, Martin D.F. ; Chao, Kai Yuan. / Mask cost reduction with circuit performance consideration for self-aligned double patterning. 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. 2011. pp. 787-792 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
@inproceedings{60b6c4283c3a40eeb7de71f1d0622b9d,
title = "Mask cost reduction with circuit performance consideration for self-aligned double patterning",
abstract = "Double patterning lithography (DPL) is the enabling technology for printing in sub-32nm nodes. In the EDA literature, researchers have been focusing on double-exposure double-patterning (DEDP) DPL for printing arbitrary 2D features where the layout decomposition problem for double exposure is an interesting graph coloring problem. But due to overlay errors, it is very difficult for DEDP to print even 1D features. A more promising DPL technology is self-aligned double patterning (SADP) for 1D design. SADP first prints dense lines and then trims away the portions not on the design by a cut mask. The complexity of cut mask is very high, adding to the skyrocketing manufacturing cost. In this paper we present a mask cost reduction method with circuit performance consideration for SADP. This is the first paper to focus on the mask cost reduction issue for SADP from a design perspective. We simplify the polygons on the cut mask, by formulating the problem as a constrained shortest path problem. Experimental results show that with a set of layouts in 28nm technology, we can largely reduce the complexity of cut polygons, with little impact on performance.",
author = "Hongbo Zhang and Yuelin Du and Wong, {Martin D.F.} and Chao, {Kai Yuan}",
year = "2011",
month = "3",
day = "28",
doi = "10.1109/ASPDAC.2011.5722296",
language = "English (US)",
isbn = "9781424475155",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
pages = "787--792",
booktitle = "2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011",

}

TY - GEN

T1 - Mask cost reduction with circuit performance consideration for self-aligned double patterning

AU - Zhang, Hongbo

AU - Du, Yuelin

AU - Wong, Martin D.F.

AU - Chao, Kai Yuan

PY - 2011/3/28

Y1 - 2011/3/28

N2 - Double patterning lithography (DPL) is the enabling technology for printing in sub-32nm nodes. In the EDA literature, researchers have been focusing on double-exposure double-patterning (DEDP) DPL for printing arbitrary 2D features where the layout decomposition problem for double exposure is an interesting graph coloring problem. But due to overlay errors, it is very difficult for DEDP to print even 1D features. A more promising DPL technology is self-aligned double patterning (SADP) for 1D design. SADP first prints dense lines and then trims away the portions not on the design by a cut mask. The complexity of cut mask is very high, adding to the skyrocketing manufacturing cost. In this paper we present a mask cost reduction method with circuit performance consideration for SADP. This is the first paper to focus on the mask cost reduction issue for SADP from a design perspective. We simplify the polygons on the cut mask, by formulating the problem as a constrained shortest path problem. Experimental results show that with a set of layouts in 28nm technology, we can largely reduce the complexity of cut polygons, with little impact on performance.

AB - Double patterning lithography (DPL) is the enabling technology for printing in sub-32nm nodes. In the EDA literature, researchers have been focusing on double-exposure double-patterning (DEDP) DPL for printing arbitrary 2D features where the layout decomposition problem for double exposure is an interesting graph coloring problem. But due to overlay errors, it is very difficult for DEDP to print even 1D features. A more promising DPL technology is self-aligned double patterning (SADP) for 1D design. SADP first prints dense lines and then trims away the portions not on the design by a cut mask. The complexity of cut mask is very high, adding to the skyrocketing manufacturing cost. In this paper we present a mask cost reduction method with circuit performance consideration for SADP. This is the first paper to focus on the mask cost reduction issue for SADP from a design perspective. We simplify the polygons on the cut mask, by formulating the problem as a constrained shortest path problem. Experimental results show that with a set of layouts in 28nm technology, we can largely reduce the complexity of cut polygons, with little impact on performance.

UR - http://www.scopus.com/inward/record.url?scp=79952972371&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79952972371&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2011.5722296

DO - 10.1109/ASPDAC.2011.5722296

M3 - Conference contribution

AN - SCOPUS:79952972371

SN - 9781424475155

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 787

EP - 792

BT - 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011

ER -