Disconnection between design and manufacturing has become a prevalent issue in modern VLSI processes. As manufacturability becomes a major concern, uncertainties from process variation and complicated rules have increased the design cost exponentially. Numerous design methodologies for manufacturability have been proposed to improve the yield. In deep submicron designs, optical proximity correction (OPC) and fill insertion have become indispensable for chip fabrication. In this paper, we propose a novel method to use these manufacturing techniques to optimize the design. We can effectively implement non-uniform wire sizing and achieve substantial performance and power improvement with very low costs on both design and manufacturing sides. The proposed method can reduce up to 42% power consumption without any delay penalty. It brings minor changes to the current design flow and no extra cost for fabrication.