Manufacturing for design: A novel interconnect optimization method

Hongbo Zhang, Liang Deng, Kai Yuan Chao, Martin D.F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Disconnection between design and manufacturing has become a prevalent issue in modern VLSI processes. As manufacturability becomes a major concern, uncertainties from process variation and complicated rules have increased the design cost exponentially. Numerous design methodologies for manufacturability have been proposed to improve the yield. In deep submicron designs, optical proximity correction (OPC) and fill insertion have become indispensable for chip fabrication. In this paper, we propose a novel method to use these manufacturing techniques to optimize the design. We can effectively implement non-uniform wire sizing and achieve substantial performance and power improvement with very low costs on both design and manufacturing sides. The proposed method can reduce up to 42% power consumption without any delay penalty. It brings minor changes to the current design flow and no extra cost for fabrication.

Original languageEnglish (US)
Title of host publicationDesign for Manufacturability through Design-Process Integration II
StatePublished - 2008
EventDesign for Manufacturability through Design-Process Integration II - San Jose, CA, United States
Duration: Feb 28 2008Feb 29 2008

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
ISSN (Print)0277-786X


OtherDesign for Manufacturability through Design-Process Integration II
Country/TerritoryUnited States
CitySan Jose, CA


  • Design for Manufacturing (DFM)
  • Interconnect optimization
  • Manufacturing for Design (MFD)
  • OPC
  • Power
  • Timing

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering


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