Manufacturability-aware physical layout optimizations

Nanometer VLSI design is greatly challanged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost functions upstream, especially at the key physical layout optimization stages such as routing and placement, to have major impacts. In this paper, we show several aspects of the true manufactruability-aware physical design, from lithography-aware routing, to redundant-via aware routing, to CMP aware florplanning and placement, and show their promises.