Manufacturability-aware physical layout optimizations

David Z. Pan, Martin D F Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Nanometer VLSI design is greatly challanged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost functions upstream, especially at the key physical layout optimization stages such as routing and placement, to have major impacts. In this paper, we show several aspects of the true manufactruability-aware physical design, from lithography-aware routing, to redundant-via aware routing, to CMP aware florplanning and placement, and show their promises.

Original languageEnglish (US)
Title of host publication2005 International Conference on Integrated Circuit Design and Technology, ICICDT
Pages149-153
Number of pages5
StatePublished - Oct 10 2005
Event2005 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States
Duration: May 9 2005May 11 2005

Publication series

Name2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Other

Other2005 International Conference on Integrated Circuit Design and Technology, ICICDT
CountryUnited States
CityAustin, TX
Period5/9/055/11/05

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Pan, D. Z., & Wong, M. D. F. (2005). Manufacturability-aware physical layout optimizations. In 2005 International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 149-153). [G2] (2005 International Conference on Integrated Circuit Design and Technology, ICICDT).